1. Field of the Invention
This invention relates to booster circuits.
2. Description of the Art
EEPROMs (electrically erasable and programmable read only memorys) are commonly known, for example, as semiconductor memories, but these memories generally require high voltage in writing and erasing.
Among EEPROMs which are generally currently used, a type which is mainly used includes a booster circuit (charge pump) to generate required high voltage within its elements.
The circuit shown in FIG. 11 has been commonly used as such booster circuit (see p. 857, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 5, Oct. 1986; and p. 150, NIKKEI ELECTRONICS, 1985. Oct. 21).
As shown in the figure, the circuit is structured with a two phase clock system using N channel MOS transistors (enhancement types are being used in this case, and also in each following example) and condensers; a supply voltage (V.sub.DD) is respectively connected to the drain and gate of an N channel MOS transistor QP1; and the source of the transistor QP1 is respectively connected to the drain and gate of an N channel MOS transistor QT1.
Similarly, N channel MOS transistors QT2-QT5 are each connected in series between the supply voltage (V.sub.DD) and a high voltage output (V.sub.PP) (five N channel MOS transistors are each connected in series in this case); the drain and gate of each transistor QT1, QT3 and QT5 are respectively connected to a clock input .phi.1 through a condenser C1; and the drain and gate of each transistor QT2 and QT4 are respectively connected to a clock input .phi.2 through a condenser C2.
In the booster circuit above, electric charge supplied from the supply voltage (V.sub.DD) through the transistor QP1 is amplified at the same time as it is shifted to the output (V.sub.PP) through each transistor QT1-QT5, by the clocks .phi.1 and .phi.2, as shown in FIG. 12.
Attention should now be paid to a problem of the above booster circuit with regard to the electric charge transfer of the N channel MOS transistor QT1 in FIG. 11. By defining the voltage of the clocks as Vc, capacity of each condenser as C, threshold voltage of the transistor QT1 as Vt (this also applies to the transistors QP1 and QT2-QT5), voltages of each of nodes N1 (the drain of the transistor QT1) and N2 (the source of the transistor QT1) before transferring the electric charge as V1 and V2, and voltage of node N2 after transferring the electric charge as Vx, then the amount of the electric charge at nodes N1 and N2 before and after transferring the electric charge can be represented as follows: EQU C(V1+Vc)+CV2=C(Vx+Vt)+VxC
Therefore, the voltage Vx of node N2 after transferring the electric charge is: EQU Vx=1/2(V1+V2+Vc-Vt)
As can be seen from the above formula, in the booster circuit in FIG. 11, because the drain and the gate of the transistor QT1 are connected to each other (used as one-directional elements like a diode by shorting the gate and the drain) the voltage Vx of node N2 after transferring the electric charge inevitably takes a value lower than the transistor QT1 by the threshold voltage Vt (that is, a loss by the threshold voltage Vt appears, inevitably).
Voltages which each node N1-N5 in FIG. 11 reaches are as follows: ##EQU1##
Therefore, as can be seen from each of the above formulae, the more the number of steps, such as the transistors QT1-QT4, the greater the loss by their threshold voltages Vt in transferring the electric charge (in this case, there is finally a voltage loss of 5Vt including the threshold voltage Vt of the transistor QP1); thus, the transfer efficiency of the electric charge significantly deteriorates (that is, too much time is taken to obtain a desired output voltage V.sub.PP). If the required output voltage V.sub.PP is high, the numbers of steps of the transistors QT1-QT5 must be naturally increased; thus, the transfer efficiency of the electric charge further deteriorates.
Also, in the case of mass production, in device fabrication, fabrication processes inevitably vary. Therefore, the values of each threshold voltage, Vt, of the transistors QP1 and QT1-QT4 or the like also vary; as a result, the value of the output voltage V.sub.PP is not stable. This degrades the reliability of the booster circuit.
In the above booster circuit, a circuit structure, shown in FIG. 13, in which elements similar to the N channel MOS transistor QP1 (transistors QP2-QP5) are connected to each node N2-N5 for supplying the supply voltage V.sub.DD, may be also possible, but still each problem described above cannot be solved. From actually examining a change of the high voltage output V.sub.PP of the booster circuit with the above circuit structure, it can be seen that the graph b in FIG. 4 shows worse booster efficiency of the output voltage V.sub.PP (too much time is taken to obtain the same voltage), compared with the graph a of a later described embodiment of the present invention (a later described embodiment of FIG. 1).